Semiconductor integrated circuit (IC) technology has experienced rapid progress including the continued minimization of feature sizes and the maximization of packing density. The minimization of feature size relies on improvement in photolithography and its ability to print smaller features or critical dimensions (CD). Especially, a lithography process to form an IC pattern to a semiconductor wafer needs to ensure that the formed IC pattern on the semiconductor wafer is aligned with the underlying patterned layer from location to location and from feature to feature. Otherwise, one or more overlay error may present, introducing various issues, such as defects, circuit failure and/or wafer scraping. For example, when a metal line is not aligned with an underlying via feature, the integrated circuit may be failed due to circuit open issue.
It is necessary to monitor overlay errors or shifting. However, in the existing technologies to check overlay error, there are various concerns and issues. For examples, overlay check is time consuming and the overlay check is not efficient (using more wafer areas by overlay marks and additional overlay metrology system). Particularly, the overlay check evaluates the overlay shifts on the overlay marks but not the overlay shifts on the real circuit. Also, the current method is to monitor overlay errors after lithography process and to check if these errors pass the criteria for going to next process stage. There is no method to real-time feedback to a lithography tool during the lithography exposure process.
Therefore, what is needed is an apparatus and a method to implement overlay monitor to address the above issues.